Timing verification method for circuits
Yazarlar (1)
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Özgün Makale
(Uluslararası alan indekslerindeki dergilerde yayınlanan tam makale)
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| Makale Dili | – | Basım Tarihi | 07-2013 |
| Makale Linki | https://patents.google.com/patent/US8484592B1/en | ||
| UAK Araştırma Alanları |
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| Özet |
| The timing verification method for stochastic networks and circuits is a computerized method that includes a Valued Sum-of-Products (VSOP) tool as an extension to Zero-sup pressed Binary Decision Diagrams (ZBDD) to compute and store paths with their corresponding lengths or statistical parameters. This method starts from source vertices and inductively builds a path database in the topological order of gates. At each node the method builds a set of partial paths that terminated that node using VSOP expressions. Path que ries are performed on all paths using VSOP operations, thereby querying the top K-most critical paths in integrated circuit networks. |
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