Timing verification method for deterministic and stochastic networks and circuits
Yazarlar (1)
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Özgün Makale
(Uluslararası alan indekslerindeki dergilerde yayınlanan tam makale)
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| Makale Dili | – | Basım Tarihi | 10-2013 |
| Makale Linki | https://patents.google.com/patent/US8555220B2/en | ||
| UAK Araştırma Alanları |
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| Özet |
| The timing verification method for deterministic and stochas tic networks and circuits is a computerized method that includes a non-enumerative path length analysis algorithm for deterministic and stochastic directed acyclic graphs (DAGs) with applications to timing verification of circuits, the algorithm computing statistical measures of path lengths without storing and/or manipulating the paths in Such net works. The timing verification method is able to compute deterministic or probabilistic costs assigned to edges, Verti ces, or both. |
| Anahtar Kelimeler |
