| Bildiri Türü |
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Bildiri Dili | İngilizce |
| Bildiri Alt Türü | Özet Metin Olarak Yayınlanan Tebliğ (Uluslararası Kongre/Sempozyum) | ||
| Bildiri Niteliği | Alanında Hakemli Uluslararası Kongre/Sempozyum | ||
| DOI Numarası | 10.1109/DSD.2003.1231947 | ||
| Kongre Adı | ProceedingFPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays | ||
| Kongre Tarihi | 01-06-2003 / 03-06-2003 | ||
| Basıldığı Ülke | Amerika Birleşik Devletleri | Basıldığı Şehir | |
| Bildiri Linki | http://ieeexplore.ieee.org/document/1231947/ | ||
| UAK Araştırma Alanları |
Mühendislik
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| Özet |
| In this paper, a randomized k-way graph partitioning algorithm is mapped onto reconfigurable hardware. The randomized algorithm relies on repetitive running of the same algorithm with different random number sequences to achieve the (near-)optimal solution. The run-time and hardware requirements of this reconfigurable solution per a random number sequence are O(|V|-K) cycles and O(|V|log|V|+|E|) gates and flip-flops, respectively. Performance is improved further at the expense of more hardware by running multiple copies of the partitioning algorithm with different random number sequences concurrently, and/or splitting a random sequence into subsequences and running them in parallel. Furthermore, in the context of this mapping, dynamic randomly configurable pattern-generation-based random number generation methods are introduced. |
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