ATPG for combinational circuits on configurable hardware
Yazarlar (2)
Doç. Dr. Fatih KOÇAN Gebze Teknik Üniversitesi, Türkiye
Daniel G. Saab
Case School of Engineering, Amerika Birleşik Devletleri
Case School of Engineering, Amerika Birleşik Devletleri
| Makale Türü | Özgün Makale (SSCI, AHCI, SCI, SCI-Exp dergilerinde yayınlanan tam makale) | ||
| Dergi Adı | IEEE Transactions on Very Large Scale Integration VLSI Systems | ||
| Dergi ISSN | 1063-8210 Wos Dergi Scopus Dergi | ||
| Dergi Tarandığı Indeksler | SCI-Expanded | ||
| Makale Dili | İngilizce | Basım Tarihi | 02-2001 |
| Kabul Tarihi | – | Yayınlanma Tarihi | 01-02-2001 |
| Cilt / Sayı / Sayfa | 9 / 1 / 117–129 | DOI | 10.1109/92.920827 |
| Makale Linki | http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=920827&openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26searchField%3DSearch+All%26queryText%3Dfatih+kocan+daniel+saab | ||
| UAK Araştırma Alanları |
Algoritmalar ve Hesaplama Kuramı
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| Özet |
| In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the D-algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock cycles: direct backward/forward implications, conflict checking, selecting next gate to propagate fault or to justify a line, decisions on gate inputs, and loading the state of the circuit after backup. In this paper, we show the feasibility of this approach in terms of hardware cost and speed and how it compares with software-based techniques. |
| Anahtar Kelimeler |
| ATPG | Combinational circuits | Concurrency | Configurable computing |
Science Direct
ATPG for combinational circuits on configurable hardware
BM Sürdürülebilir Kalkınma Amaçları
| Atıf Sayıları | |
| Web of Science | 5 |
| Google Scholar | 17 |